参考文献
本书共引用 20 条文献，涵盖处理器体系结构、微架构、RISC-V 指令集、VLSI 电路以及经典教科书五个主题。条目按作者姓氏首字母排序；每条结尾的锚点支持从正文 \cite{key} 位置直接跳转定位。
参考文献格式接近 GB/T 7714，但考虑到 Web 阅读体验作了若干简化：书籍标题用斜体，期刊和会议论文集用斜体，作者多于三人时以 et al. 缩写。
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Krste Asanović, and David A. Patterson. Instruction Sets Should Be Free: The Case For RISC-V. In EECS Department, UC Berkeley, Technical Report. 2014.
Robert H. Dennard et al. Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions. IEEE Journal of Solid-State Circuits, 9(5):256–268. 1974.
Sarah Harris, and David Harris. Digital Design and Computer Architecture: RISC-V Edition. Morgan Kaufmann. 2022.
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Daniel A. Jiménez, and Calvin Lin. Dynamic Branch Prediction with Perceptrons. In HPCA. 2001.
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Paul Kocher et al. Spectre Attacks: Exploiting Speculative Execution. In IEEE S&P. 2019.
Moritz Lipp et al. Meltdown: Reading Kernel Memory from User Space. In USENIX Security. 2018.
Gordon E. Moore. Cramming More Components onto Integrated Circuits. Electronics, 38(8). 1965.
David A. Patterson, and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface: RISC-V Edition. 2nd edition. Morgan Kaufmann. 2020.
André Seznec. A Case for (Partially) TAgged GEometric History Length Branch Prediction. In Journal of Instruction-Level Parallelism. 2006.
John Paul Shen, and Mikko H. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. Waveland Press. 2013.
James E. Smith, and Gurindar S. Sohi. The Microarchitecture of Superscalar Processors. Proceedings of the IEEE, 83(12):1609–1624. 1995.
Robert M. Tomasulo. An Efficient Algorithm for Exploiting Multiple Arithmetic Units. In IBM Journal of Research and Development, pp. 25–33. 1967.
Andrew Waterman, and Krste Asanović. The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA. RISC-V International. 2019.
Andrew Waterman, and Krste Asanović. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture. RISC-V International. 2019.
Neil H. E. Weste, and David Money Harris. CMOS VLSI Design: A Circuits and Systems Perspective. 4th edition. Addison-Wesley. 2011.
Yinan Xu et al. Towards Developing High Performance RISC-V Processors Using Agile Methodology. In MICRO. 2022.